Transmitter and receiver

ABSTRACT

An interleave frame is formed by combining slots corresponding to the same slot number in each frame when interleave process is performed in a super frame, and the data are read out along row or column direction (i.e. readout direction) and the data are written along the direction opposite to the readout direction in the same memory.

TECHNICAL FIELD

The present invention relates to an interleaving technique involved indigital modulation and demodulation, especially to a transmitter and areceiver capable of performing the unified interleave and deinterleavewithout employing an interleave method corresponding to a multiplexingscheme based on each transmission mode when implementing multiplextransmission combining a plurality of transmission modes with differenterror endurance.

BACKGROUND ART

FIG. 4 shows a multiplexed signal structure in which a frame structureis comprised of one frame including 48 slots and one super frame isstructured by eight frames, for example. Here, a slot is a memory areafor storing a packet consisting of 204 bytes adding a 16-byte RS(204,188) error correction code to a 188-byte MPEG-2 TS packet. In digitaltransmission using a broadcasting satellite, it is assumed that theslots of the same number of each frame in a super frame, may use thesame type transmission mode including the modulation scheme and errorcorrection code, and four types of transmission modes can be used atmaximum in one super frame. In addition, the transmission modes in thesuper frame are flexibly varied by reporting those modes from atransmitting side to a receiving side by using a control signal called aTMCC signal contained in the second previous super frame.

FIG. 5 shows the structure of a modulated signal generated from themultiplexed signal. In this case, the multiplexed data is subjected tointerleaving in the transmitter side and deinterleaving in the receivingside in order to derive the full power of Reed-Solomon (RS) codes,typical external codes, by distributing burst errors which occur whenthe number of bit errors in the transmission channel are beyond theerror correcting capability of a Viterbi decoder or a trellis decoderused for error correction in the receiver. For example, interleaving ofdepth eight is implemented by forming interleave frames at every eightslots using the same type transmission mode in a frame, and by readingout of the column the data of the interleave frames written into a rowin a two dimensional memory. (When the number of the slots using thesame type transmission mode is less than eight in a frame, or the numberof the remaining slots is less than eight when the interleave frames areformed every eight slots in sequence, the interleave frame is structuredin addition to slots of a frame which will be described later.

As structural examples, the implementing interleave process will now bedescribed with reference to FIGS. 6 and 7. FIG. 6 shows an example inwhich 46 slots are transmitted by TC-8 PSK and one slot is transmittedby QPSK subjected to convolutional encoding with a coding rated of ½,and further, one slot is regarded as a dummy slot. FIG. 7 shows anexample in which 44 slots are transmitted by TC-8 PSK and one slot istransmitted by BPSK subjected to convolutional encoding with a codingrate of ½, and further, three slots are regarded as dummy slots.

In either example, as for the one slot transmitted by QPSK or BPSK, oneinterleave frame is formed in one super frame. To match the timing ofsignals after the interleaving, a first-in-first-out (FIFO) memory forstoring data with a length of the super frame {(data length of assignedslots)-(length of the interleave frame)} is necessary for the greaterassigned slot number (in the above example, the 46 slots or 44 slotsdata transmitted by the TC-8 PSK).

Since the interleave frame is 204×8 bytes, a FIFO memory is comprised of204×46×8−204×8=73440 bytes in the example of FIG. 6, and shows a FIFOmemory is comprised of 204×44×8−204×8=70176 bytes in the example of FIG.7, thus performing the interleave process by once storing the dataamount close to one super frame every each transmission mode.

However, the capacity of the FIFO memory changes according to theassigned slot number for each of transmission modes in the frame, and acontroller controlling the interleave process should be needed becauseaddress control is changed according to the change of the capacity ofthe FIFO memory, thereby complicating a circuit structure.

SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide atransmitter and a receiver implementing an interleave process simplywithout changing the circuit configuration by changing the assigned slotnumber according to the transmission mode in each frame.

In the first aspect of the present invention, there is provided atransmitter applicable to a transmission system capable of transmittingdigital data (called the transmission coded signal), which are encodedby using different types of error correction codes and modulated bydifferent types of modulation with schemes, as packet units in themultiplexed data with a frame structure consisting of N packets, saidtransmitter performing interleaving of a super frame unit, andcomprising:

means for forming an interleave frame by combining packets correspondingto the same slot number in each frame;

write means for sequentially writing data according to a frame number ofthe interleave frame into a two-dimensionally arrangeable memory along arow or a column direction; and

readout means for sequentially reading out the written data from thetwo-dimensionally arrangeable memory along a column or row directiondifferent from the row or column direction of said write means.

In the second aspect of the present invention, there is provided areceiver applicable to a transmission system capable of transmittingdigital data (called transmission coded signal), which are encoded byusing different types of error correction codes and are modulated bydifferent types of modulation techniques, as packet unit in themultiplexed data with a frame structure consisting of N packets, saidreceiver performing deinterleaving of a super frame unit, andcomprising:

means for forming a deinterleave frame by combining packetscorresponding to the same slot number in each frame;

write means for sequentially writing data according to a frame number ofthe deinterleave frame into a two-dimensionally arrangeable memory alongthe column or row direction corresponding to the readout direction of aninterleave process during transmission; and

readout means for sequentially reading out the written data from thetwo-dimensionally arrangeable memory along the row or column directiondifferent from the column or row direction of said write meanscorresponding to the writing direction of the interleave process duringtransmission.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic perspective view showing a frame structure as anembodiment according to the present invention;

FIG. 2 is a diagram showing a data arrangement in frames according tothe present invention;

FIG. 3 is a diagram showing an example of an interleave process;

FIG. 4 is a schematic perspective view showing a conventional framestructure;

FIG. 5 is a diagram showing a data arrangement in conventional frames;

FIG. 6 is a block diagram showing a conventional transmission process;and

FIG. 7 is a block diagram showing another conventional transmissionprocess.

BEST MODE FOR CARRYING OUT THE INVENTION

A preferred embodiment of the present invention will be described indetail with reference to the drawings.

The present invention relates to an interleave process applicable todigital transmission. In particular, in a transmission system that cantransmit mixed data comprising of different types of transmission modesas packet units in the multiplexed data with a frame structureconsisting of N packets, an interleave frame is formed by combiningslots corresponding to the same slot number in each frame, and theinterleave process is performed every interleave frame, thus simplyperforming the interleave process under the same memory control eventhough various types of transmission modes in mixed data may betransmitted.

This example refers to a reading and writing process of a transmissionsystem in that interleave in the transmitter and deinterleave in thereceiver, which is opposite to the interleave can be performed. Aconcrete example will be described as follows.

FIG. 1 shows the structure of a single super frame 10. The super frame10 is structured by eight frames 20. Each frame 20 consists of 48 slots30. These slots 30 are structured by various types of signals, such asmultiplexed signals including video, audio and associated informations,a frame synchronizer, TMCC and super frame synchronizer. One slot 30consists of (1+187+16) bytes. FIG. 2 shows the frames 20 in the superframe 10 sequentially arranged.

The processings performed by the transmission and reception of thesystem will be described with reference to FIGS. 3(a) to 3(e).

FIG. 3(b) shows a memory 40 capable of being arrayed in two dimensions.First, when FIG. 3 is assumed to be a process of the transmitter, FIG.3(a) shows the data arrangement in the super frame 10 before interleave.In contrast, FIG. 3(c) shows the data arrangement after interleave.FIGS. 3(d) to 3(e) schematically shows the data read process from thememory 40.

In the present example, using the memory 40, the interleave process asto the data in the super frame 10 of FIG. 1 is performed. This is tosay, the data is written into the memory 40 in the horizontal direction(along the row direction), and the data is read out from the memory 40in the vertical direction (along the column direction). A more detailedexample follows.

As an example, when slot number is 1, the interleave is performed as tothe slots #1 of the first to eighth frames 20, and the data is writteninto the two-dimensional memory 40 along the row direction sequentiallyfrom the first slot of the first frame 20. In the present example, theith data of each frame 20 (shaded area) is written every 203-byte datawidth.

After the data is written, the data is read out from the memory 40 alongthe column direction perpendicular to the row direction.

Table 1 shows a sequential arrangement of the actual read addresses andthe data read addresses of the first slots according to each frame.Here, the numerals indicate frame-bytes.

TABLE 1 Read addresses of first slots (frame-byte) Second 203th Startbyte byte (frame-byte) (frame-byte) (frame-byte) first frame 1-1  2-1 3-26  second frame 4-26  5-26  6-51  third frame 7-51  8-51  1-77 fourth frame 2-77  3-77  4-102 fifth frame 5-102 6-102 7-127 sixth frame8-127 1-128 2-153 seventh frame 3-153 4-153 5-178 eighth frame 6-1787-178 8-203

By doing the readout process, interleave can be performed independentlyof the assigned slot number every each frame.

Furthermore, by exchanging the readout direction and the writedirection, deinterleave can be performed in the receiver (i.e. thedeinterleave process can be performed by writing the data according tothe readout direction of the interleave and can be performed by readingout the data according to the write direction of the interleave).

On the other hand, when FIG. 3 is assumed to be a process of thereceiver, FIG. 3(c) shows the data before the deinterleave process, andFIG. 3(a) shows the data after the deinterleave process.

INDUSTRIAL APPLICABILITY

As described above, according to the present invention, an interleaveframe is formed by combining slots corresponding to the same slot numberin each frame when the interleave process is performed in a super frame,and the data are read out along the row or column direction (i.e.readout direction) and the data are written along the direction oppositeto the readout direction in the same memory. This makes it possible toobviate complicated memory address controllers according to transmissionmode structures in the interleave or deinterleave process, therebyenabling a uniform control in any case.

What is claimed is:
 1. A transmitter applicable to a transmission systemcapable of transmitting digital data, said digital data being encoded byusing an error correction code and being modulated by a modulationscheme, said digital data being transmitted as packet units inmultiplexed data with a frame structure consisting of N packets, saidtransmitter performing interleaving of a super frame unit, andcomprising: means for forming an interleave frame by combining packetscorresponding to the same slot number in each frame; write means forsequentially writing data according to a frame number of the interleaveframe into a two-dimensionally arrangeable memory along a row or columndirection; and readout means for sequentially reading out the writtendata from the two-dimensionally arrangeable memory along a column or rowdirection different from the row or column direction of said writemeans.
 2. A receiver applicable to a transmission system capable oftransmitting digital data, said digital data being encoded by using anerror correction code and being modulated by a modulation technique,said digital data being transmitted as packet units in the multiplexeddata with a frame structure consisting of N packets, said receiverperforming deinterleaving of a super frame unit, and comprising: meansfor forming a deinterleave frame by combining packets corresponding tothe same slot number in each frame; write means for sequentially writingdata according to a frame number of the deinterleave frame into atwo-dimensionally arrangeable memory along a column or row directioncorresponding to a readout direction of an interleave process duringtransmission; and readout means for sequentially reading out the writtendata from the two-dimensionally arrangeable memory along a row or columndirection different from the column or row direction of said write meansand corresponding to a writing direction of the interleave processduring transmission.